Path transistor circuit and method for designing the same, a device and method for optimizing logic circuits, and a computer product

ABSTRACT

A path transistor circuit comprises a plurality of path transistors connected in parallel. Same input signal is inputted into the sources of these path transistors. Continuities of these path transistors is controlled by a plurality of control signals having an exclusive relationship therebetween. A plurality of buffers respectively drive the drive segments including at least the path transistors and wirings. The drive segments being a plurality of divided ranges each having an equal potential.

FIELD OF THE INVENTION

[0001] The present invention relates to a path transistor circuit usedas a selector employing path transistors, a path transistor circuitdesign method, a logic circuit optimization device used to optimizebuffering in designing a logic circuit, a logic circuit optimizationmethod and a computer-readable recording medium in which a computerprogram which when executed on a computer realizes the method accordingto the present invention.

BACKGROUND OF THE INVENTION

[0002] In the recent semiconductor LSI (Large Scale Integrated Circuit)field, a method for designing a logic circuit using path transistors hasbeen widely utilized. Especially, A logic circuit composition methodusing a binary decision diagram plays a significant role in separating alogic circuit into select logics and putting the design of a logiccircuit using path transistors to practical use. In addition, it isknown that in a path transistor logic circuit, the number of normallyused transistors is smaller than the number of CMOS (Complementary MetalOxide Semiconductor) gates, thereby facilitating realizing low powerconsumption and high integration.

[0003] On the other hand, potential problems with the use of a pathtransistor include that the path transistor lacks in a force for drivingother transistors such as a CMOS circuit. Due to this, conventionally, aplurality of stages of path transistors are connected to thereby causewaveform deformation of an electric signal, thus rather sacrificingtiming performance. In these circumstances, demand for providing meansand a method capable of overcoming these disadvantages more effectivelythan before rises.

[0004] Recently, with the progress of the high integration of asemiconductor integrated circuit, attention is increasingly paid to apath transistor capable of realizing high integration with low powerconsumption. A technique of this type has been frequently used indesigning mainly a memory or a programmable logic array. Since thedesign of a logic circuit employing a binary decision diagram theory waspublished, this technique has been employed positively with a view tohigher integration, lower power consumption and higher speed.

[0005] The binary decision diagram theory is a theory for realizinglogic circuit design in which a logic function is translated to anappropriate binary tree by using the binary decision diagram and theresultant tree is replaced by a path transistor selector having a pairof exclusive select inputs and one output. Conventionally, logiccomposition and circuit optimization are carried out based on the binarydecision diagram theory.

[0006] For example, Japanese Patent Application Laid-Open No. 9-6821 (tobe referred to as “Publication 1” hereinafter) discloses a method ofefficiently probing a binary decision diagram. According to this method,temporary circuits of AND and OR circuits are composed from a logicfunction and grouped based on the input correlation, and the binarydecision graph is probed while optimizing a combination of groups tothereby replace the circuits by a path transistor selector.

[0007] Meanwhile, it has become conventionally possible to easily createa logic by applying path transistors to a logic circuit. Althougheffective in solving a select logic, the path transistor has anessential disadvantage in that a signal driving force should be suppliedfrom another CMOS gate. This disadvantage is, therefore, one factorwhich makes circuit design difficult.

[0008] Further, in designing logic, if a circuit logically composedusing a path transistor cannot be actually used due to the occurrence ofa waveform deformation, it is necessary to change circuit arrangement.To do so, a method for intentionally mixing an optimal combination ofCMOS logics into a logic circuit including path transistors, is adopted.

[0009] Japanese Patent Application Laid-Open No. 9-321146 (to bereferred to as “Publication 2” hereinafter) and Japanese PatentApplication Laid-Open No. 10-200394 (to be referred to as “Publication3” hereinafter) disclose the above-stated method as well as a method foroptimizing a circuit area, delay time and power consumption. Namely,Publication 2 discloses a method including registering both logicallyequivalent CMOS circuit and path transistor circuit cells in a libraryand combining them according to required conditions so as to allow themixture of the CMOS logic and the path transistor logic and toautomatically optimize the circuit area, delay time and powerconsumption.

[0010] Publication 3 discloses a method including replacing portionshaving inputs fixed to“0” and “1” of a path transistor type logiccircuit created based on the binary decision diagram theory by NAND andNOR circuits of a logically equivalent CMOS circuits and adjusting thecircuits in light of the performance and required values of the overallcircuits.

[0011] As disclosed by Publications 2 and 3, it is conventionallyimpossible to satisfy required performance only with the path transistorlogic and the CMOS logic is, therefore, still employed to the ordinarydesign of logic. Nevertheless, the path transistors are often used onlyfor a path transistor selector circuit capable of making most use of thefeatures of the CMOS theory.

[0012]FIG. 23A shows a design example 1 of a conventional logic circuit(or the path transistor selector circuit in this case). The pathtransistor selector circuit shown therein consists of n NMOS pathtransistors t0 to tn provided at an input side and an inverter inv0 anda voltage holding PMOS transistor pt0 provided at an output side. Inputsignals s0 to sn are inputted into the input terminals i0 to in of thesepath transistors t0 to tn, respectively. In addition, the continuitiesof the path transistors t0 to tn are controlled by control signals se10to se1n inputted into gates g0 to gn, respectively. Here, the level ofonly one of the control signals se10 to se1n is H (active) and thelevels of the remaining control signals are L.

[0013] The drains d0 to dn of the path transistors t0 to tn,respectively, are connected to the input terminal of the inverter inv0.The inverter inv0 inverts the output signal of any one of the pathtransistors t0 to tn and outputs the inverted signal as an output signalo0. This inverter inv0 exists at a node n0. The voltage holding PMOStransistor pt0 is intended to hold voltage. The drain dp of the voltageholding PMOS transistor pt0 is connected to the input terminal of theinverter inv0 and the gate gp thereof is connected to the outputterminal of the inverter inv0.

[0014] If the level of the control signal se10 is set at H and those ofthe other control signals se1 to se1n are set t L, then only the pathtransistor t0 becomes continuous and an input signal s0 is therebyselected from among the input signals s0 to sn. As a result, the inputsignal s0 is inverted by the inverter inv0 and then outputted as anoutput signal o0.

[0015] Additionally, a path transistor selector circuit shown in FIG.23B is conventionally used. In FIG. 23B, a selector function is realizedby employing complementary transfer gates C0 to Cn instead of the pathtransistors t0 to tn shown in FIG. 23A. It is noted that the pathtransistor selector circuit shown in FIG. 23B is not provided with avoltage holding PMOS transistor pt0 and in this case (like shown in FIG.23B) any CMOS gate (AND, OR, etc . . . ) can be switched instead ofinverter inv0 (Not shown).

[0016] In the meantime, as already stated above, the conventional designhas disadvantage in that the load capacity of the path transistorselector circuit dynamically changes according to the values of thecontrol signals se10 to se1n shown in FIG. 23A. Namely, if the level ofthe control signal se10 is H and the levels of the control signals se11,se12, . . . and seln are L, then a load capacity Ct to be driven fromthe input terminal i0 becomes the sum of parasitic capacities Cs0 andCd0 at the source and drain d0 of the path transistor t0 through whichthe input signal s0 passes, a gate capacity Cinv0 at the gate of theinverter inv0, a parasitic capacity Cdp at the drain dp of the voltageholding PMOS transistor pt0 and drain capacities Cd1 to Cdn at thedrains d1 to dn of the respective path transistors t1 to tn. This loadcapacity Ct is expressed by the following equation (1):

Ct=Cs 0+(Cd 0+Cd 1+. . . +Cdn)+Cdp+Cinv 0 . . .  (1)

[0017] On the other hand, if the level of the control signal se10 is L,a load capacity Ct′ to be driven from the input terminal i0 becomes aparasitic capacity Cs0 at the source of the path transistor t0 andexpressed by the following equation (2):

Ct′=Cs0 . . .  (2)

[0018] Conventionally, therefore, the load capacity of the pathtransistor selector circuit dynamically changes (to the load capacity Ctor the load capacity Ct′) according to the values (H level or L level)of the control signals se10 to se1n. Thus, a problem arises particularlywhen handling the path transistor selector circuit as some units.

[0019] Namely, as shown in FIG. 9, if one wiring (signal line) is usedas the input line of two or more path transistors (in case of FIG. 9,path transistors t0, t2, t4 and t6) , the magnitude of the load capacityat the input terminal varies according to the patterns of the controlsignals controlling the continuities of the respective path transistors.In FIG. 9, the wiring of an input signal a0 is connected to therespective sources of the four path transistors t0, t2, t4 and t6.

[0020] Here, in a case where only the path transistor t0 selects theinput signal a0 among the path transistors t0, t2, t4 and t6, i.e., thelevel of the control signal sa0 is H and the levels of the controlsignals sa1, sa2 and sa3 are L, then the load capacity is the sum of thecapacity of a load connected to the node n0 and the parasitic capacitiesat the respective source of the path transistors t2, t4 and t6.

[0021] On the other hand, in a case where all of the path transistorst0, t2, t4 and t6 select the input signal a0, i.e., the levels of thecontrol signals sa0, sa1, sa2 and sa3 are H, then the loads of theinverters inv0 to inv3 connected to the nodes n0 to n3, respectively andthe path transistors t1, t3, t5 and t7 which do not select the inputsignal a0 are to be driven by one buffer (not shown) for the inputsignal a0 in a front stage, with the result that the circuit becomesdisadvantageously unbalanced.

[0022] Such a phenomenon always occurs irrespectively of the number ofconnections of the path transistor selector circuit and the number ofcontrol signals (or the number of path transistors) of the pathtransistor selector circuit. In case of the constitution in which pathtransistor selector circuits employing path transistors are connected inparallel as data path constituent circuits such as shifters and dataalign circuits, in particular, the number of long data transmissionwirings for connecting the path transistor selector circuits is greaterthan the number of wirings in an ordinary logic circuit and the loadcapacity thereof thereby increases. Due to this, in view of thedynamically changing load capacity and the load resistance caused by thelong wirings, it is required to consider, for example, minimizing loadcapacity and load resistance as much as possible in a design phase.

[0023]FIG. 24 shows a design example 2 of the conventional logic circuitintended to increase the response speed of the circuit. In FIG. 24,parts corresponding to those in FIG. 2 are denoted by the same referencesymbols as those in FIG. 2. In FIG. 24, inverters ia0 and ib0, . . . andia3 and ib3 are provided at the source sides of path transistors t0 tot7, respectively and inverters ic0, ic1 . . . and ic3 are provided atoutput sides thereof. The method of the design example 2 can be expectedto advantageously improve the response speed of the circuit. However,due to the increase of the number of logic stages and devices, apackaging area and power consumption disadvantageously increase.

[0024] Furthermore, conventionally, if logic circuit packaging operationis automated, it is disadvantageously difficult to handle a parasiticload capacity at an input terminal in a cell design phase. If a net listis composed and a path transistor circuit employing path transistors issimply replaced by a cell, an input driving buffer may be inadvertentlymade large in scale, thus disadvantageously providing a quite imbalancedcircuit.

[0025] As can be understood from the above, the load capacitydynamically changing according to the control logic (control signalpatterns) is one factor which makes it difficult to ensure a drivingforce even in designing a cell base. This also causes the increase of apacking area and power consumption and the reduction of the responsespeed due to the waveform deformation of a signal. Moreover, in case ofcharacterizing a circuit by the delay, load capacity and the like of apath transistor selector circuit employing path transistors, the circuitis normally required to be characterized by the load capacity Ctexpressed by the equation (1), i.e., the worst value, so as to avoid theabove disadvantages. It is, therefore, expected to be difficult toadjust the circuit to avoid racing.

[0026] Other objects and features of this invention will become apparentfrom the following description with reference to the accompanyingdrawings.

SUMMARY OF THE INVENTION

[0027] It is an object of the present invention to provide a pathtransistor circuit, a path transistor circuit design method, a logiccircuit optimization device, a logic circuit optimization method and acomputer-readable recording medium recording a logic circuitoptimization program capable of easily optimizing the buffering of apass transistor circuit (logic circuit) employing path transistors andobtaining a logic circuit excellent in electric characteristics.

[0028] In the path transistor circuit according to one aspect of thepresent invention, a plurality of path transistors are connected inparallel, same input signal is inputted into the input terminals ofthese path transistors, and continuities of the plurality of pathtransistors is controlled by a plurality of control signals having anexclusive relationship therebetween. Further, a plurality of buffers areprovided for driving the drive segments including at least the pluralityof path transistors and wirings, the drive segments being a plurality ofdivided ranges each having an equal potential.

[0029] Thus, the plurality of control signals have an exclusiverelationship therebetween, i.e., the control signals do not becomeactive simultaneously, a circuit is divided into a plurality of rangeseach having an equal potential as drive segments to thereby drive thedrive segments independently using buffers, respectively. As a result,it is possible to easily optimize buffering and obtain a path transistorcircuit excellent in electric characteristics, compared with aconventional circuit.

[0030] The logic circuit optimization device according to another aspectof the present invention comprises a logic specification indication unitwhich indicates logic specifications so that a plurality of controlsignals controlling continuities of the plurality of path transistors,respectively, have an exclusive relationship therebetween; a celllibrary unit which registers a plurality of cell data used to design thelogic circuit; and an optimization unit which conducts a logiccomposition based on the logic specifications and the cell data, and foroptimizing buffering in the logic circuit.

[0031] Thus, the logic specification indication unit indicates logicspecifications so that a plurality of control signals have an exclusiverelationship therebetween, i.e., the control signals do not becomeactive simultaneously, and logic composition and the optimization ofbuffering are conducted based on the logic specifications and cell data.As a result, it is possible to easily optimize the buffering of a logiccircuit employing path transistors and obtain a logic circuit excellentin electric characteristics.

BRIEF DESCRIPTION OF THE DRAWINGS

[0032]FIG. 1 is a block diagram showing the constitution of oneembodiment according to the present invention;

[0033]FIG. 2 shows an example of a grouping description part data 12shown in FIG. 1;

[0034]FIG. 3 shows a cell library 700 used in the embodiment;

[0035]FIG. 4 is an explanatory view for a CMOS logic circuit cell A usedin the embodiment;

[0036]FIG. 5 is an explanatory view for a path transistor selector cellD used in the embodiment;

[0037]FIG. 6A and FIG. 6B are explain the operation of the embodiment;

[0038]FIG. 7 is an explanatory view for the operation of the embodiment;

[0039]FIG. 8 is a flow chart for describing the operation of theembodiment;

[0040]FIG. 9 is an explanatory view for a design example 1 in theembodiment;

[0041]FIG. 10 is an explanatory view for a design example 1 in theembodiment;

[0042]FIG. 1A to FIG. 11C are for explaining a design example 2 in theembodiment;

[0043]FIG. 12A and FIG. 12B are for explaining a design example 3 in theembodiment;

[0044]FIG. 13A and FIG. 13B are for explaining a design example 4 in theembodiment;

[0045]FIG. 14 is an explanatory view for a design example 4 in theembodiment;

[0046]FIG. 15 is an explanatory view for a design example in theembodiment;

[0047]FIG. 16 is an explanatory view for a modified example of theembodiment;

[0048]FIG. 17 is an explanatory view for a modified example of theembodiment;

[0049]FIG. 18 is an explanatory view for a modified example of theembodiment;

[0050]FIG. 19 is an explanatory view for a modified example of theembodiment;

[0051]FIG. 20 is an explanatory view for a modified example of theembodiment;

[0052]FIG. 21 is an explanatory view for a modified example of theembodiment;

[0053]FIG. 22 is a block diagram showing a modified example of theembodiment;

[0054]FIG. 23A and FIG. 23B show a design example 1 of a conventionallogic circuit; and

[0055]FIG. 24 shows a design example 2 of a conventional logic circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0056] A preferred embodiment of a path transistor circuit, a pathtransistor circuit design method, a logic circuit optimization device, alogic circuit optimization method and a computer-readable recordingmedium recording a logic circuit optimization program according to thepresent invention, will now be explained with reference to theaccompanying drawings.

[0057]FIG. 1 is a block diagram showing the constitution of oneembodiment according to the present invention. In FIG. 1, a logicspecification indication section 1 indicates logic specificationsrelating to a to-be-designed logic circuit. To be specific, the logicspecification indication section 1 inputs a behavior/net list 10 andspecification data 11 as logic specifications. The behavior/net list 10is behavior and a net list described in HDL (Hardware DescriptionLanguage) relating to a to-be-designed logic circuit. As the behaviorstate transition and the like relating to the logic circuit aredescribed. As the net list, component information, wiring connectioninformation, positional information and the like are described. Oneexample of the logic circuit described herein may be a path transistorselector circuit already stated above.

[0058] The specification data 11 is expected value data on the input andoutput of the logic circuit. A drive segment indication section 2indicates directly or indirectly grouped drive segments constituting thelogic circuit to the same node or net according to a certain rule (e.g.,the exclusive conditions of control signals). To be specific, the drivesegment indication section 2 inputs grouped description part data 12corresponding to the drive segment. FIG. 2 shows examples of the groupeddescription part data 12. In FIG. 2, as examples of grouped descriptionpart data 12, grouped description part data 12 A(example 1), groupeddescription part data 12B (example 2) and grouped description part data12C (example 3) are shown.

[0059] The grouped description part data 12A defines information on aterminal designation group 1 (control terminals a to d), a terminaldesignation group 2 (control signals e to h), a terminal designationgroup 3, . . . designating terminals constituting a drive segment. Thegrouped description part data 12B defines information on a terminaldesignation group 1 (instance A, control signal terminal a, . . . andinstance D, control signal terminal d), a terminal designation group 2,a terminal designation group 3, constituting the drive segment. Thegrouped description part data 12C defines information on an instancedesignation group 1 (instances a to d), an instance designation group 2,an instance designation group 3, . . . The three types of groupeddescription part data 12A, 12B and 12C stated above may be recordedtogether in one recording region of a storage device (not shown) orrecorded in a plurality of recording regions, respectively.

[0060] Here, as one embodiment, analyses as to logic composition,automatic wiring, and the electric characteristics (delay, waveform,power) of the logic circuit are executed based on a cell library 700shown in FIG. 3. In FIG. 3, parts corresponding to the respective partsshown in FIG. 1 are denoted by the same reference symbols as those inFIG. 1. Data (to be referred to as “cell data” hereinafter) forrealizing cells which are considered to be the basic circuits in thedesign of a logic circuit such as circuits combining logic elements areregistered in the cell library 700 according to a cell (fixed pattern)method.

[0061] Cell data for realizing a CMOS logic circuit cell A shown in, forexample, FIG. 4, include cell data CELL-A11 on the net list, cell dataCELL-A12 (input/output logic operations) on input/output logicoperations, cell data CELL-A21 on mask data, cell data CELL-A22 oninput/output terminal positions, cell data CELL-A31 on input/outputloads and resistances, cell data CELL-A32 on delay time and drivingforce, . . . These cell data CELL-A11, CELL-A12, . . . correspond tolibraries shown in FIG. 3.

[0062] Namely, the cell data CELL-A11 is registered in a CMOS logiccircuit net list library 110 (see FIG. 3) and the cell data CELL-A12 isregistered in a CMOS logic circuit input/output logic operation library120 (see FIG. 3). Likewise, the cell data CELL-A21 is registered in aCMOS logic circuit mask data library 210 and the cell data CELL-A22 isregistered in a CMOS logic circuit input/output terminal positionlibrary 220. The cell data CELL-A31 is registered in a CMOS logiccircuit input/output load/resistance library 310 and the cell dataCELL-A32 is registered in a CMOS logic circuit delay time/driving forcelibrary 320.

[0063] Similarly, cell data for realizing a path transistor selectorcell D shown in FIG. 5 include cell data CELL-D11 on the net list, celldata CELL-D12 on input/output logic operations, cell data CELL-D21 onmask data, cell data CELL-D22 on input/output terminal positions, celldata CELL-D36 on input/output loads and resistances during assertion,cell data CELL-D37 on input/output loads and resistances duringnegation, cell data CELL-D38 on delay time and driving force, . . .These cell data CELL-D11, CELL-D12, . . . correspond to libraries shownin FIG. 3.

[0064] Namely, the cell data CELL-D11 is registered in a path transistorselector circuit net list library (not shown) of a net list creationpath transistor selector cell library 150 (see FIG. 3). The cell dataCELL-D12 is registered in a path transistor selector circuitinput/output logic operation library (not shown) of the net listcreation path transistor selector cell library 150.

[0065] Likewise, the cell data CELL-D21 is registered in a pathtransistors selector circuit mask data library (not shown) of a layoutcreation path transistor selector cell library 250. The cell dataCELL-D22 is registered in a path transistor selector input/outputterminal position library (not shown) of the layout creation pathtransistor selector cell library 250. The cell data CELL-D36 isregistered in a path transistor selector library 360. The cell dataCELL-D37 is registered in a path transistor selector library 370. Thecell data CELL-D38 is registered in a path transistor selector library380.

[0066] As can be seen, the cell library 700 consists of a net listcreation CMOS logic circuit cell library 100, a net list creation pathtransistor selector cell library 150, a layout creation CMOS logiccircuit cell library 200, a layout creation path transistor selectorcell library 250, an electric characteristic analysis CMOS logic circuitcell library 300 and an electric characteristic analysis path transistorselector cell library 350 (see FIG. 1).

[0067] The net list creation CMOS logic circuit cell library 100 is alibrary in which data on a cell (CMOS logic circuit) for creating a netlist. The library 100 consists of a CMOS logic circuit net list library110 and a CMOS logic circuit input/output logic operation library 120.In the CMOS logic circuit net library 110, the cell data CELL-A11,CELL-B11, CELL-C11, . . . for creating the net list of the CMOS logiccircuit are registered. In the CMOS logic circuit input/output logicoperation library 120, the cell data CELL-A12, CELL-B12, CELL-C12, . . .on the input/output logic operation of the CMOS logic circuit areregistered.

[0068] On the other hand, the net list creation path transistor selectorcell library 150 is the same in structure as the net list creation CMOSlogic circuit cell library 100. The library 150 consists of a pathtransistor selector circuit net list library and a path transistorselector circuit input/output logic operation library (both of whichlibraries are not shown). While the net list creation CMOS logic circuitcell library 100 consists of data on a plurality of cells for the CMOSlogic circuit, the net list creation path transistor selector celllibrary 150 consists of data on a plurality of cells for the pathtransistor selector circuits. Here, the path transistor selector circuitmeans a selector circuit employing the path transistors.

[0069] The layout creation CMOS logic circuit cell library 200 is alibrary in which data on a plurality of cells on the layout of the maskpattern of the CMOS logic circuit. The library 200 consists of a CMOSlogic circuit mask data library 210 and a CMOS logic circuitinput/output terminal position library 220.

[0070] In the CMOS logic circuit mask data library 210, the cell dataCELL-A21, CELL-B21, CELL-C21, . . . on the mask pattern of the CMOSlogic circuit are registered. In the CMOS logic circuit input/outputterminal position library 220, the cell data CELL-A22, CELL-B22,CELL-C22, . . . on the positions of the input/output terminals of theCMOS logic circuit are registered.

[0071] On the other hand, the layout creation path transistor selectorcell library 250 is the same in structure as the layout creation CMOSlogic circuit cell library 200. The layout creation path transistorselector cell library 250 consists of path transistor selector circuitmask data and a path transistor selector circuit input/output positionlibrary (both of which are not shown). While the layout creation CMOSlogic circuit cell library 200 consists of data on a plurality of cellsfor the CMOS logic circuit, the layout creation path transistor selectorcell library 250 consists of data on a plurality of cells for the pathtransistors elector circuit.

[0072] The electric characteristic analysis CMOS logic circuit celllibrary 300 is a library in which data on a plurality of cells on theelectric characteristics (delay, waveform, power and the like) of theCMOS logic circuit. The library 300 consists of the CMOS logic circuitinput/output load and resistance library 310 and the CMOS logic circuitdelay time and driving force library 320.

[0073] In the CMOS logic circuit input/output load and resistancelibrary 310, the cell data CELL-A31, CELL-B31, CELL-C31, . . . on theinput/output loads and resistances of the CMOS logic circuit areregistered. In the CMOS logic circuit delay time and driving forcelibrary 320, the cell data CELL-A32, CELL-B32, CELL-C32, . . . on thedelay time and driving force of the CMOS logic circuit are registered.

[0074] On the other hand, the electric characteristic analysis pathtransistor selector cell library 350 is a library in which data on aplurality of cells on the electric characteristics (delay, waveform,power and the like) of the path transistor selector circuit. The library350 consists of the path transistor selector libraries 360, 370 and 380.The electric characteristics include those during the assertion of thepath transistor and during the negation thereof.

[0075] Here, consideration will be given to a case where the pathtransistor selector circuits each having n select inputs, i.e., pathtransistors t0 to tn as shown in FIG. 6A are cells A1 to Am,respectively shown in FIG. 6B and an input signal in0 is inputted to therespective input terminals i0 in common. In this case, the maximum valueCt of the load capacity of the input terminal i0 of the cell A1 isexpressed by the equation (1) and the minimum value Ct′ of the loadcapacity thereof is expressed by the equation (2).

[0076] To characterize a cell, the maximum value Ct and delay time Ttare usually adopted. If m cells, i.e., cells A1 to Am are connected inparallel as shown in FIG. 6B, however, the load capacity m•Ct iserroneously recognized as the magnitude of the load of the inputterminal i0 and the electric characteristics can not be analyzedprecisely. In that case, the state of the control signal for each pathtransistor is checked and, if the transistor is not continuous, the loadcapacity is set at the minimum value Ct′. During the assertion of thepath transistors, the path transistor selector library 360 (see FIG. 3)corresponding to the maximum value Ct is employed. During the negationof the path transistors, the path transistor selector library 370corresponding to the minimum value Ct′ is employed.

[0077] In the path transistor selector library 360, the cell dataCELL-D36, CELL-E36, CELL-F36, . . . on the input/output loads andresistances of the path transistor select circuit during the assertionof the path transistors are registered. In the path transistor selectorlibrary 370, the cell data CELL-D37, CELL-E37, CELL-F37, . . . on theinput/output loads and resistances of the path transistor selectorcircuit during the negation of the path transistors are registered. Inthe path transistor selector library 380, the cell data CELL-D38,CELL-E38, CELL-F38, . . . on the delay time and driving force of thepath transistor selector circuit are registered.

[0078] Returning to FIG. 1, the logic composition processing section 3creates a composed net list 800 by executing a logic compositionprocessing for composing a combination of a plurality of cells based onthe specification data 11 from the logic specification indicationsection 1, the behavior/net list 10, the grouped description part data12 from the drive segment indication section 2, the net list creationCMOS logic circuit cell library 100, the net list creation pathtransistor selector cell library 150, the electric characteristicanalysis CMOS logic circuit cell library 300 and the electriccharacteristic analysis path transistor selector cell library 350.Normally, the composed net list 800 does not include information on theelectric characteristics of wirings between cells.

[0079] A delay, waveform and power analysis section 4 analyzes electriccharacteristics (delay, waveform, power) relating to the composed netlist 800 using the electric characteristic analysis CMOS logic circuitcell library 300 and the electric characteristic analysis pathtransistor selector cell library 350, and provides delay, waveform,power consumption analysis estimation result data 810 as an analysisresult. Here, if analyzing the delay of the path transistor selectorcircuit shown in FIG. 7, the delay, wave form and power analysis section4 performs analysis as to a path (wiring) indicated by a thick lineshown therein.

[0080] An automatic layout/wiring processing section 5 creates layoutdata 820 on the logic circuit using the composed net list 800, thelayout creation CMOS logic circuit cell library 200 and the layoutcreation path transistor selector cell library 250. The layout data 820includes all physical characteristics such as those of wirings betweencells.

[0081] A layout data conversion section 6 converts the layout data 820into mask pattern data 830 and physical characteristics (of wirings andthe like) inclusive net list 840. The mask pattern data 830 is data onthe mask pattern in case of forming a logic circuit on a semiconductorsubstrate. The physical characteristics (of wirings and the like)inclusive net list 840 include physical characteristics of wirings andthe like.

[0082] A delay, waveform and power analysis section 7 analyzes electriccharacteristics (delay, waveform and power) relating to the physicalcharacteristics (of wirings and the like) inclusive net list 840 usingthe electric characteristic analysis CMOS logic circuit cell library 300and the electric characteristic analysis path transistor selector celllibrary 350, and provides delay, waveform and power consumption analysisdesign value data 850 as an analysis result.

[0083] Next, the operation will be described with reference to a flowchart shown in FIG. 8. While the present invention is applied to a logiccircuit optimization device serving as a CAD (Computer Aided Design)device, design examples 1 to 5 (see FIGS. 9 to 15) of the logic circuitusing this logic circuit optimization device will be described first.

[0084] Design Example 1

[0085] First, description will be given to a design example 1 fordesigning a path transistor selector circuit shown in FIG. 10 obtainedby optimizing a path transistor selector circuit (logic circuit) shownin FIG. 9. The path transistor selector circuit shown in FIG. 9 has fournodes n0 to n3. From these nodes, selected input signals are outputtedas output signals o0 to o3 through inverters inv0 to inv3, respectively.At the node n0, path transistors t0 and t1 connected in parallel, theinverter inv0 and a voltage holding PMOS transistor pt0 are arranged.

[0086] The continuities of these path transistors t0 and t1 arecontrolled by control signals sa0 and sb0, respectively and one of inputsignals a0 and b0 is selected. Namely, if the level of the controlsignal sa0 is H. the path transistor t0 becomes continuous and the inputsignal a0 is selected. If the level of the control signal sb0 is H, thepath transistor t1 becomes continuous and the input signal b0 isselected. Here, the control signals sa0 and sb0 has an exclusiverelationship therebetween, i.e., if the level of one signal is H, thelevel of the other is L and the levels of the both signals do not becomeH simultaneously.

[0087] At the node n1, path transistors t2 and t3 connected in parallel,the inverter inv1 and a voltage holding PMOS transistor pt1 arearranged. The continuities of these path transistors t2 and t3 arecontrolled by control signals sa1 and sb1, respectively and one of inputsignals a0 and b1 is selected. Namely, if the level of the controlsignal sa1 is H, the path transistor t2 becomes continuous and the inputsignal a0 is selected. If the level of the control signal sb1 is H, thepath transistor t3 becomes continuous and the input signal b1 isselected. Here, the control signals sa1 and sb1 has an exclusiverelationship therebetween, i.e., if the level of one signal is H, thatof the other is L and the levels of the both signals do not become Hsimultaneously.

[0088] At the node n2, path transistors t4 and t5 connected in parallel,the inverter inv2 and a voltage holding PMOS transistor pt2 arearranged. The continuities of these path transistors t4 and t5 arecontrolled by control signals sa2 and sb2, respectively, and one ofinput signals a0 and b2 is selected. Namely, if the level of the controlsignal sa2 is H, the path transistor t4 becomes continuous and the inputsignal a0 is selected. If the level of the control signal sb2 is H, thepath transistor t5 becomes continuous and the input signal b2 isselected. Here, the control signals sa2 and sb2 have an exclusiverelationship therebetween, i.e., if the level of one signal is H, thelevel of the other is L and the levels of the both signals do not becomeH simultaneously.

[0089] At the node n3, path transistors t6 and t7 connected in parallel,the inverter inv3 and a voltage holding PMO transistor pt3 are arranged.The continuities of these path transistors t6 and t7 are controlled bycontrol signals sa3 and sb3 and one of input signals a0 and b3 isselected. Namely, if the level of the control signal sa3 is H, the pathtransistor t6 becomes continuous and the input signal a0 is selected. Ifthe level of the control signal sb3 is H, the path transistor t7 becomescontinuous and the input signal b3 is selected. Here, the controlsignals sa3 and sb3 have an exclusive relationship therebetween, i.e.,if the level of one signal is H, that of the other is L and the levelsof the both signals do not become H simultaneously.

[0090] Here, in the path transistor selector circuit shown in FIG. 9,the input signal a0 is a common input signal inputted to the pathtransistors t0, t2, t4 and t6. Due to this, it is necessary to drive theload of the load capacity of the worst value seen from the inputterminal of the input signal a0 using one buffer (not shown) . Namely,in the path transistor selector circuit showed in FIG. 9, a bufferhaving an enough and spare driving force (i.e., a buffer ensuring anexcessive driving force) is used, which buffer is not preferable inlight of reducing power consumption and a packaging area. Further, inthe path transistor selector circuit, the levels of all the controlsignals sa0, sa1, sa2 and sa3 are often set at H level simultaneously.That is, these control signals sa0, sa1, sa2 and sa3 do not satisfy anexclusive relationship therebetween.

[0091] In this embodiment, a range (path transistor(s), wiring(s),inverter(s) , voltage holding PMOS transistor(s), node(s)) driven by onebuffer in the path transistor selector circuit and having the samepotential is defined as a drive segment. For example, if only the pathtransistor t0 shown in FIG. 9 is continuous and one buffer is connectedto the input terminal of the input signal a0, then the drive segmentcorresponds to a range including the elements (the path transistor t0,the inverter inv0, the voltage holding PMOS transistor pt0) on the noden0, the wirings connected to those elements and wirings connected to therespective sources of the path transistors t2, t4 and t6.

[0092] Furthermore, if both the path transistors t0 and t2 arecontinuous and one buffer is connected to the input terminal of theinput signal a0, the drive segment corresponds to a range includingelements (the path transistor t0, the inverter inv0, the voltage holdingPMOS transistor pt0) on the node 0 and wirings connected to theseelements, elements (the path transistor t2, the inverter inv1, thevoltage holding PMOS transistor pt1) on the node n1 and wiringsconnected to these elements, and wirings connected to the respectivesources of the path transistors t4 and t6.

[0093] In this way, in the path transistor selector circuit shown inFIG. 9, the control signals sa0, sa1, sa2 and sa3 do not have anexclusive relationship therebetween. Due to this, the drive segmentdynamically changes between the drive segment in a case where the levelof the control signal sa0 is H and only the path transistor t0 iscontinuous, and the drive segment in a case where the level of thecontrol signal sa0 is H, that of the control signal sa1 is H and boththe path transistors t0 and t2 are continuous.

[0094] Accordingly, in the path transistor selector circuit shown inFIG. 9, the drive segment dynamically changes according to the patternsof the control signals and the load capacity of the load which should bedriven by one buffer, therefore, dynamically changes. To deal with sucha dynamic change of the load capacity, a buffer capable of driving theload with the load capacity of the worst value (maximum value) is usedin the path transistor selector circuit in FIG. 9. In addition, the loadcapacity changes since the control signals sa0, sa1, sa2 and sa3 do nothave an exclusive relationship therebetween.

[0095] Considering this, the path transistor selector circuit which hasbeen optimized as shown in FIG. 10 is designed so that control signalssa0, sa1, sa2 and sa3 have an exclusive relationship therebetween (i.e.,only one control signal is at H level and the other control signals areat L level at the same time). Besides, a range including the pathtransistors t0 and t2, wirings and the like, is defined as one drivesegment, whereas a range including the path transistors t4, t6, wiringsand the like, is defined as the other drive segment. One drive segmentis driven by a buffer B0 and the other drive segment is driven by abuffer B1. Namely, the path transistor selector circuit shown in FIG. 9has one drive segment, whereas the path transistor shown in FIG. 10 hastwo drive segments.

[0096] Further, in the one drive segment, the buffer B0 optimum fordriving the sum of a load relating to a path transistor (e.g., pathtransistor t0) selected by the control signal, a load relating to anunselected path transistor (e.g., path transistor t2) and a loadrelating to wirings, is provided. Here, the sum of the plural loadsstated above is a value estimated as a worst value. Accordingly,compared with the buffer (not shown) for the path transistor selectorcircuit shown in FIG. 9, the buffer B0 does not need to ensure anexcessive driving force but it suffices to have a driving forcenecessary and sufficient (effective driving force).

[0097] Likewise, in the other drive segment, the buffer B1 optimum fordriving the sum of a load relating to a path transistor (e.g., pathtransistor t4) selected by the control signal, a load relating to anunselected path transistor (e.g. path transistor t6) and a load relatingto wirings, is provided. Here, the sum of the plural loads stated aboveis a value estimated as a worst value. Accordingly, compared with thebuffer for the path transistor selector circuit(not shown) in FIG. 9,the buffer B1 does not need to ensure an excessive driving force but itsuffices to have a driving force necessary and sufficient (effectivedriving force).

[0098] As can be understood from the above, in the design example 1, thebuffers B0 and B1 each having an optimum driving force are provided onthe logic circuit as shown in FIG. 10, thereby optimizing the logiccircuit. It is noted that the optimization method in the design example1 (FIG. 10) can be conducted irrespectively of the number of selectionsof the selector, the number of selectors connected in parallel, thenumber of input signals of the same selector, the type of pathtransistors (NMOS, PMOS, transmission gate) and wiring length.

[0099] Next, description will be given to the design example 1 fordesigning the path transistor selector circuit (see FIG. 10) withreference to the flow chart shown in FIG. 8. In a step SA1, a pluralityof cells constituting the cell library 700 shown in FIG. 3 are created.In a step SA2, logic and physical characteristic data on the respectivecells are collected.

[0100] In a step SA3, it is judged whether or not the to-be-designedlogic circuit is a path transistor selector circuit. If this judgmentresult is “Yes”, in a step SA4, the net list creation path transistorselector cell library 150, the layout creation path transistor selectorcell library 250 and the electric characteristic analysis pathtransistor selector cell library 350 shown in FIG. 3 are created.

[0101] On the other hand, if the judgment result of the step SA3 is “No”in a step SA5, the net list creation CMOS logic circuit cell library100, the layout creation CMOS logic circuit cell library 200 and theelectric characteristic analysis CMOS logic circuit cell library 300shown in FIG. 3 are created. In a step SA6, the libraries created ineither the step SA4 or step SA5 are registered in the cell library 700.

[0102] In a step SA7, the behavior/net list 10 described in HDL and thespecification data 11 are created as logic specifications. As a result,the logic specification indication section 1 indicates the logicspecifications (the behavior/net list 10 and the specification data 11).The logic specifications indicated here are intended to realize the pathtransistor selector circuit shown in FIG. 10 and include the exclusiverelationship between the control signals, area, delay time, powerconsumption and the like as already described above.

[0103] In a step SA8, grouped description part data 12 (see FIG. 2) onthe groups (drive segments) of the path transistor selector circuit iscreated based on cell and terminal information. As a result, the drivesegment indication section 2 indicates grouping based on the groupeddescription part data 12. The drive segments here include the pathtransistors t0 and t1, the path transistors t2 and t3, the pathtransistors t4 and t5, and the path transistors t6 and t7 shown in FIG.10.

[0104] In a step SA9, the logic composition processing section 3designates the fixation and optimization of the circuit and performs alogic composition based on the specification data 11 from the logicspecification indication section 1, the behavior/net list 10, thegrouped description part data 12 from the drive segment indicationsection 2, the net list creation path transistor selector cell library150 and the electric characteristic analysis path transistor selectorcell library 350. As a result, the logic composition processing section3 passes the logic composition result to the delay, waveform and poweranalysis section 4 and to the automatic layout and wiring processingsection 5 as the composed net list 800.

[0105] In a step SA10, the delay, waveform and power analysis section 4analyzes electric characteristics (delay, waveform and power) relatingto the composed net list 800 using the electric characteristic analysispath transistor selector cell library 350. In a step SA11, the delay,waveform and power analysis section 4 judges whether or not the electriccharacteristic analysis result satisfies the required specifications. Ifthis judgment result is “No”, the electric characteristic specificationsare reviewed and optimized so as to satisfy the required specificationsin steps SA7, SA8 and SA9.

[0106] That is, in the step SA7, a logic structure employing the pathtransistor selector is reviewed and the overall logic structure isreviewed. In the step SA8, the grouping of the path transistor selectoris reviewed. Also, in the step SA9, optimization other than grouping ofthe path transistor selector is conducted. As a result, in a step SA10,electric characteristics relating to the composed net list 800 afterreview and optimization are analyzed.

[0107] On the other hand, if the judgment result of the step SA11 is“Yes”, the automatic layout and wiring processing section 5 createslayout data 820 on the logic circuit conforming to a design rule basedon the composed net list 800 and the layout creation path transistorselector cell library 250. In a step SA13, the layout conversion section6 converts the layout data 820 into the physical characteristic (ofwirings and the like) inclusive net list 840 and then passes the list840 to the delay, waveform and power analysis section 7.

[0108] Consequently, the delay, waveform and power analysis section 7analyzes the electric properties (delay, waveform, power) relating tothe physical characteristic (of wirings and the like) inclusive net list840 using the electric characteristic analysis path transistor selectorcell library 350. In a step SA14, the delay, waveform and power analysissection 7 judges whether or not the electric characteristic analysisresult satisfies the required specifications. If this judgment result is“No”, the layout and wirings are optimized in a step SA12 andprocessings after a step SA13 are executed.

[0109] On the other hand, if the judgment result SA14 is “Yes”, i.e.,the physical characteristic (of wirings and the like) inclusive net list840 satisfies the required specifications relating to the electriccharacteristics, then the layout data conversion section 6 converts thelayout data 820 into the mask pattern data 830. Thereafter, based on themask pattern data 830, the logic circuit shown in FIG. 10 is formed onthe semiconductor substrate.

[0110] Design Example 2

[0111] Next, description will be given to a design example 2 fordesigning a path transistor selector circuit shown in FIGS. 11B and 11Cobtained by optimizing a path transistor selector circuit (logiccircuit) shown in FIG. 1A. The path transistor selector circuit(prototype) shown in FIG. 11A has two nodes, i.e., n0 (selector SEL0)and n1 (selector SEL1) From the respective nodes, selected input signalsare outputted as output signals o0 and o1.

[0112] At the node n0, path transistors t0 to t3 connected in parallel,an inverter inv0 and a voltage holding PMOS transistor pt0 are arranged.The continuities of these path transistors t0 to t3 are controlled bycontrol signals sa0, sb0, sc0 and sd0, respectively and one of inputsignals a0, b0, c0 and d0 is selected. For example, if the level of thecontrol signal sa0 is H, then the path transistor t0 becomes continuousand the input signal a0 is selected and outputted, as the output signalo0, to a logic circuit 900 in the later stage through the inverter inv0.

[0113] At the node n1, path transistors t4 to t7 connected in parallel,an inverter inv1 and a voltage holding PMOS transistor pt1 are arranged.The input signal a0 is an input signal common to the path transistors t0and t4. The continuities of these path transistors t4 to t7 arecontrolled by control signals sa1, sb1, sc1 and sd1, respectively andone of input signals a0, b1, c1 and d1 is selected. For example, if thelevel of the control signal sa1 is H, then the path transistor t4becomes continuous and the input signal a0 is selected. The input signala0 is outputted, as an output signal o1, to the logic circuit 900 in thelater stage through the inverter inv1.

[0114] Here, in the logic circuit shown in FIG. 1A, the levels of thecontrol signals sa0 and sa1 often become H simultaneously. In that case,the problem occurs that a load capacity to be driven increases and thatoptimum buffering cannot be conducted. To avoid this problem, in thedesign example 2, the behavior/net list 10, the specification data 11and the grouped description part data 12 shown in FIG. 1 are created soas to intentionally ensure the exclusive relationship between thecontrol signal sa0′ and sa1′ as shown in FIG. 11B.

[0115] By doing so, the levels of the control signals sa0′ and sa1′ donot become H simultaneously and optimum buffering can be realized,thereby reducing a packaging area and improving delay time and powerconsumption. That is to say, by intentionally recomposing the selectedlogics so as to obtain control signals which have an exclusiverelationship therebetween for the purpose of creating independent drivesegments (selectors SEL0 and SEL1) to optimize buffering, the operationcharacteristics of the path transistor circuit improves.

[0116] Further, in the design example 2, as shown in FIG. 11C, thebehavior/net list 10, the specification data 11 and the groupeddescription part data 12 are created so that the input signal sa0 maynot be inputted into two drive segments (selectors SEL0 and SEL1). It isnoted that the logic circuits shown in FIGS. 11B and 11C are designedaccording to the flow chart shown in FIG. 8. The optimization method inthe design example 2 (FIGS. 11B and 11C) can be realized irrespectivelyof the number of selections of the selectors, the number of selectorsconnected in parallel, the number of input signals of a single selector,the type of path transistors (NMOS, PMOS, transmission gate) and wiringlength.

[0117] Design Example 3

[0118] Next, description will be given to a design example 3 fordesigning a path transistor selector circuit shown in FIG. 12B obtainedby optimizing a path transistor selector circuit (logic circuit) shownin FIG. 12A. The path transistor selector circuit (prototype) shown inFIG. 12A consists of four selectors SEL0 to SEL4. Each of the selectorsSEL0 to SEL4 is a three-input, one-output type selector and consists ofa plurality of path transistors (not shown). It is noted that FIG. 12Adoes not show the control signals of the path transistors. Also, one ofthe input signals of the selector SEL0 is an input signal common to theother selectors SEL1 to SEL4.

[0119] In the design example 3, if it is necessary to optimize (improvebuffering) of a path PS1 relating to the selector SEL1 shown in FIG. 12Aand a path PS 2 relating to the selector SEL2 and it is not necessary tooptimize the other paths, then the path transistor selector circuitshown in FIG. 12B is designed.

[0120] Namely, in the design example 3, the selectors SEL1 and SEL2required to be optimized are partially cut as a drive segment and theseselectors SEL1 and SEL2 are subjected to the optimization in either thedesign example 1 or design example 2 described above, thereby selectinga buffer B for realizing optimum buffering. In the design example 3, thebehavior/net list 10, the specification data 11 and the groupeddescription part data 12 (see FIG. 1) for realizing the optimization arecreated. It is noted that the path transistor selector circuit shown inFIG. 12B is designed according to the flow chart shown in FIG. 8.

[0121] Design Example 4

[0122] Next, description will be given to a design example 4 fordesigning a path transistor selector circuit shown in FIG. 13B obtainedby optimizing a path transistor selector circuit (logic circuit) shownin FIG. 13A. The path transistor selector circuit (prototype) shown inFIG. 13A is a data alignment circuit for fetching data of [0:63] bitsshown in FIG. 14 as effective bits in units of one byte (eight bits) .In FIG. 13A, among [0:63] bits to be outputted, selectors SEL0, SEL32,SEL48 and SEL56 corresponding to [0] bit, [32] bit, [48] bit and [56]bit, respectively are shown and selectors corresponding to the remainingbits are not shown.

[0123] The selector SEL0 selects either input bit [0] or ‘0’ data basedon a control signal and outputs the selected one as an output bitout[0]. The selector SEL32 selects one of input bits in [0], [32] and‘0’ data based on a control signal and outputs the selected one as anoutput bit out [32]. The selector SEL48 selects one of input bits in[0], [16], [48] and ‘0’ data and outputs the selected one as an outputbit out[48].

[0124] Further, the selector SEL56 selects one of input bits in [0 ],[8], [24], [56] and ‘0’ data and outputs the selected one as an outputbit out [56]. Here, the input bit [0] is an input bit common to theselectors SEL0, SEL32, SEL48 and SEL56.

[0125] The data alignment circuit shown in FIG. 13A is capable ofoutputting output data of five patterns in all according to controlpatterns 1 to 5 shown in FIG. 14. Namely, in the control pattern 1, ‘0’is selected by the control circuit in the selectors SEL0, SEL32 andSEL48. In the selector SEL56, the input bit [0] is selected by thecontrol signal and outputted as an output bit [56]. Accordingly, in thecontrol pattern 1, as shown in FIG. 14, output data of [0:55]=‘0’ and[56:63]=one-byte data, are outputted.

[0126] Further, in the control pattern 4, with the output bit out [32]as the boundary of a drive segment, output data of [0:31]=four-byte data(byte0 to byte3 of input data), [32:63]=four-byte data (byte0 to byte3of input data) are outputted. Namely, in the control pattern 4, both theselectors SEL0 and SEL32 select the input bit in [0]. Due to this, thecontrol signals of the both selectors do not have an exclusiverelationship therebetween. In that case, it is difficult to realizeoptimum buffering and the specifications do not satisfy the requiredspecifications with regard to area, delay time, power consumption andthe like.

[0127] Considering this, in the design example 4, as shown in FIG. 13B,with the output bit out [32] as the boundary of a drive segment, abuffer B1 corresponding to the selectors SEL0 and SEL32 and a buffer B2corresponding to the selectors SEL48 and SEL56 are provided and thebuffers B1 ad B2 conduct buffering independently of each other, therebymaking it possible to conduct optimum buffering.

[0128] Further, in the design example 4, the behavior/net list 10, thespecification data 11 and the grouped description part data 12 (seeFIG. 1) for realizing the optimization are created. It is noted that thepath transistor selector circuits shown in FIG. 13B are designedaccording to the flow chart shown in FIG. 8. The optimization method inthe design example 4 (see FIG. 13B) is also applicable to a barrelshifter circuit or the like used for bit operation and realizedirrespectively of the number of selections, the number of selectorsconnected in parallel, the number of input signals of a single selector,the type of path transistors (NMOS, PMOS and transmission gate) andwiring length.

[0129] Design Example 5

[0130] In the design examples 1 to 4, description has been given about acase of microscopically optimizing the logic circuit while payingattention to the exclusive relationship between the control signals. Asshown in FIG. 15, the optimization method is also applicable to a pathtransistor selector circuit 1200 and a data path 1300 used for a memoryblock 1100 such as a RAM macro or a register array.

[0131] The latter case will be described hereinafter as a design example5. In the memory block 1100, data read/write is controlled by the pathtransistor selector circuit 1200. This path transistor selector circuit1200 is obtained by making a group of drive segments a macro group. Thecircuit 1200 selects read/write select pattern data using controlsignals divided in an exclusive manner and outputs the selected data tothe memory block 1100. This path transistor selector circuit 1200 canobtain the same advantages as those in the design examples 1 to 4.

[0132] Further, the data path 1300 is provided at the output side of thememory block 1100 and has the same functions as those of the pathtransistor selector circuit shown in FIG. 13A and FIG. 13B. That is tosay, the data path 1300 conducts data alignment and bit operation forshift operation and the like to the read data, according to controlsignals divided in an exclusive manner. In the design example 4, thebehavior/net list 10, the specification data 11 and the groupeddescription part data 12 (see FIG. 1) for realizing the optimization ofthe path transistor selector circuit 1200 and the data path 1300, arecreated. It is noted that the path transistor selector circuit 1200 andthe data path 1300 shown in FIG. 15 are designed according to the flowchart shown in FIG. 8.

[0133] One embodiment according to the present invention has beendescribed in detail so far, with reference to the accompanying drawings.It should be noted that concrete constitution examples of the presetinvention are not limited to this embodiment and that any design changesand the like within the range of the scope of the present invention areincluded in the invention.

[0134] For example, as a modified example 1 of one embodiment, an NANDcircuit shown in FIG. 16 instead of each of the selectors x₀ to X₃ shownin FIG. 10 may be provided. In the NAND circuit shown in FIG. 16, pathtransistors t0, t1 and an inverter inv1 are provided at the input sideof a node n0 and an inverter inv0 and a voltage holding PMOS transistorpt0 are provided at the output side of the node n0. The continuities ofthe path transistors t0 and t1 are controlled by a control signal se10.The drains of the respective path transistors t0 and t1 are connected tothe common node n0.

[0135] An input terminal i0 at the source side of the path transistor t0is set to have a potential equal to the potential of the input terminalat the source side of the other path transistor through a wiring (notshown) . In the NAND circuit shown in FIG. 16, the inverter inv1 may beprovided at the control signal se10-side of the path transistor t0, thesource side of the path transistor t0 may be grounded and the sourceside of the path transistor t1 maybe set as the input terminal i0.

[0136] Furthermore, as a modified example 2 of one embodiment statedabove, an NOR circuit shown in FIG. 17 instead of each of the selectorsx₀ to X₃ shown in FIG. 10 may be provided. In the NOR circuit shown inFIG. 17, path transistors t0, t1 and an inverter inv1 are provided atthe input side of a node n0 and an inverter inv0 is provided at theoutput side of the node n0. The continuities of the path transistors t0and t1 are controlled by a control signal se10. The drains of therespective path transistors t0 and t1 are connected to the common noden0.

[0137] An input terminal i0 at the source side of the path transistor t0has a potential equal to the potential of an input terminal at thesource side of the other path transistor through a wiring (not shown).In the NOR circuit shown therein, the inverter inv1 may be provided atthe transistor t1 side, the source side of the path transistor t0 mayhave a predetermined potential and the source side of the pathtransistor t1 may be set as an input terminal i0.

[0138] Moreover, as a modified example 3 of one embodiment stated above,a circuit shown in FIG. 18 instead of each of the selectors x₀ to X₃shown in FIG. 10 may be provided. In the circuit shown in FIG. 18, pathtransistors t0 to tn are provided at the input side of a node n0 and aninverter inv0 and a voltage holding PMOS transistor pt0 are provided atthe output side of the node n0.

[0139] The continuities of these path transistors t0 to tn arecontrolled by control signals se10 to se1n, respectively. An inputterminal i0 at the source side of the path transistor t0 is set to havea potential equal to the potential of an input terminal at the sourceside of the other path transistor through a wiring (not shown). Thedrains of the respective path transistors t0 to tn are connected to thecommon node n0. In the circuit shown in FIG. 18, the path transistor t2or path transistor t3 may be omitted.

[0140] Furthermore, as a modified example 4 of one embodiment statedabove, a multi-stage circuit shown in FIG. 19 instead of each of theselectors x₀ to X₃ shown in FIG. 10 may be provided. In the circuitshown in FIG. 19, path transistors t0 to tn, a path transistor tm, aninverter inv1 and a voltage holding PMOS transistor pt1 are arranged atthe input side of a node n0 and an inverter inv0 and a voltage holdingPMOS transistor pt0 are arranged at the output side of the node n0.

[0141] The circuit shown therein is intended to reduce a load capacityseen from the input terminals i0 and i1. The continuities of the pathtransistors t0 to tn and the path transistor tm are controlled bycontrol signals se10 to se1n and selm, respectively. The circuit showntherein may be constituted to dispense with pull-up circuits (theinverter inv1 and the voltage holding PMOS transistor pt1).

[0142] As a modified example 5 of one embodiment stated above, a circuitshown in FIG. 20 instead of the buffer B0 and the circuits x₀ and x₁(buffer B1, circuits x₂ and X₃) shown in FIG. 10 maybe arranged. Thecircuit shown in FIG. 20 consists of a buffer B0, selectors MUX0 toMUX2. The selector MUX0 consists of path transistors t00, t01, t02 andt03 provided at the input side of a node n0 and an inverter inv0 aid avoltage holding PMOS transistor pt0 provided at the output side of thenode n0. The continuities of these path transistors t00, t01, t02 andt03 are controlled by control signals se100, se101, se102 and se103,respectively.

[0143] The selector MUX1 consists of path transistors t10, t11, t12 andt13 provided at the input side of the node n1 and an inverter inv1 and avoltage holding PMOS transistor pt1 provided at the output side of thenode n1. The continuities of these path transistors t10, t11, t12 andt13 are controlled by control signals se110, se111, se112 and se113,respectively.

[0144] The selector MUX2 consists of path transistors t20, t21, t22 andt23 provided at the input side of the node n2 and an inverter inv2 and avoltage holding PMOS transistor pt2 provided at the output side of thenode n2. The continuities of these path transistors t20, t21, t22 andt23 are controlled by control signals se12O, se121, se122 and se123,respectively.

[0145] In the circuit shown in FIG. 20, the sources s00, s11 and s21 ofthe respective path transistors t00, t11 and t21 are connected to acommon buffer B0 through wirings. Here, the control signals se100, se111and se121 controlling the continuities of the path transistors t00, t11and t21, respectively, have an exclusive relationship therebetween.Therefore, if the level of one control signal out of these controlsignals se100, se111 and se121 is H, the levels of the other controlsignals are L.

[0146] Capacitors C00, C01 and a resistance R0 correspond to thecapacities and resistance of a wiring connecting the buffer B0 to thesource s11 of the path transistor t11. Likewise, capacitors C10, C11 anda resistance R1 correspond to the capacities and resistance of a wiringconnecting the source s11 of the path transistor t11 to the source s21of the path transistor t21. In the modified example 5, description hasbeen given while assuming that control signals having an exclusiverelationship there between are control signals se100, se111 and se121.The other combination of control signals is also applicable.

[0147] In the modified example 5 (see FIG. 20), if wirings connectingthe buffer B0 to the sources s00, s11 and s21 of the respective pathtransistors t00, t11 and t21 are long, the load capacity seen from theside of the buffer B0 increases. To avoid this, the wirings may be cutoff in the middle so as to reduce the load capacity by utilizing theexclusive relationship among the control signals se100, se111 and se121.This constitution will be described hereinafter as a modified example 6.

[0148]FIG. 21 is an explanatory view for the modified example 6 of oneembodiment already stated above. In FIG. 21, parts corresponding tothose in FIG. 20 are denoted by the same reference symbols as those inFIG. 20. In FIG. 21, a path transistor ta is interposed in the middle ofa wiring (at a buffer B0 side) connecting a buffer B0 to the source s11of a path transistor t11. The continuity of the path transistor ta iscontrolled by a control signal se100 (inversion) inverted from a controlsignal se100. Therefore, if the level of the control signal se100 is Hand the path transistor t00 is continuous, the level of the controlsignal se100 (inversion) is L and the path transistor ta is cut off.Thus, the wiring capacity and resistance seen from the side of thebuffer B0 are reduced by those of the downstream part of the pathtransistor ta.

[0149] An inverter invp and a voltage holding PMOS transistor ptpconstitute a pull-up circuit and are connected to one end of aresistance R0. This pull-up circuit is intended to improve the electriccharacteristics relating to wirings when the path transistor ta iscontinuous.

[0150] Also, in the circuit shown in FIG. 21, a path transistor tb isinterposed in the middle (at a source s11 side) of a wiring connectingthe source s11 of the path transistor t11 to the source s21 of the pathtransistor t21. The continuity of the path transistor tb is controlledby a control signal se111 (inversion) inverted from a control signalse111. Therefore, if the level of the control signal se111 is H and thepath transistor t00 is continuous, the level of the control signal se111(inversion) is L and the path transistor tb is cut off. Thus, the wiringcapacity and resistance seen from the side of the buffer B0 are reducedby those of the downstream part of the path transistor tb.

[0151] Furthermore, as a modified example 7 of one embodiment alreadystated above, a logic circuit optimization program for realizing theabove-stated functions may be recorded on a computer readable recordingmedium 1500 shown in FIG. 22 and the logic circuit optimization programrecorded on this recording medium 1500 may be read and executed by acomputer 1400, thereby designing and optimizing the logic circuit.

[0152] The computer 1400 shown in FIG. 22 consists of a CPU 1401executing the logic circuit optimization program, an input device 1402such as a keyboard and a mouse, an ROM (Read Only Memory) 1403 storingvarious data, an RAM (Random Access Memory) 1404 storing operationparameters and the like, a reading device 1405 reading the logic circuitoptimization program from the recording medium 1500, an output device1406 such as a display and a printer, and a bus BU connecting therespective constituent elements of the computer 1400.

[0153] The CPU 1401 reads the logic circuit optimization programrecorded on the recording medium 1500 through the reading device 1405,executes the logic circuit optimization program and thereby designs andoptimizes the logic circuit. The recording medium 1500 may be not only aportable type recording medium such as an optical disk, a floppy disk ora hard disk, but also a transmission medium, such as a network,temporarily holding data.

[0154] In one embodiment stated above, the logic circuit optimizationdevice (CAD) shown in FIG. 1 has been described. The present inventionis also applicable to a macro design such as a full-custom macro designor a semi-custom macro design. Accordingly, the path transistor selectorcircuit itself described in the embodiment is also contained in thepresent invention.

[0155] As explained above, according to one embodiment of the presentinvention, a plurality of control signals have an exclusive relationshiptherebetween, i.e., the control signals do not become activesimultaneously, a circuit is divided into a plurality of ranges eachhaving an equal potential as drive segments to thereby drive the drivesegments independently using the buffers B0 and B1 (see FIG. 10),respectively. Thus, it is possible to easily optimize buffering and toobtain a logic circuit excellent in electric characteristics comparedwith a conventional circuit.

[0156] Furthermore, a plurality of control signals have an exclusiverelationship therebetween, i.e., the control signals do not becomeactive simultaneously, a circuit is divided into a plurality of rangeseach having an equal potential as drive segments to thereby drive thedrive segments independently using buffers, respectively. Thus, thepresent invention can advantageously, easily optimize buffering andobtain a logic circuit excellent in electric characteristics, comparedwith a conventional circuit.

[0157] Furthermore, the logic specification indication unit indicateslogic specifications so that a plurality of control signals have anexclusive relationship therebetween, i.e., the control signals do notbecome active simultaneously, and logic composition and the optimizationof buffering are conducted based on the logic specifications and celldata. Thus, the present invention can advantageously optimize thebuffering of a logic circuit employing path transistors and obtain alogic circuit excellent in electric characteristics.

[0158] Furthermore, in a logic specification indication step, logicspecifications are indicated so that a plurality of signals have anexclusive relationship therebetween, i.e., the control signals do notbecome active simultaneously, and logic composition and the optimizationof buffering are conducted based on the logic specification and celldata. Thus, the present invention can advantageously optimize thebuffering of a logic circuit employing path transistors and obtain alogic circuit excellent in electric characteristics.

[0159] Although the invention has been described with respect to aspecific embodiment for a complete and clear disclosure, the appendedclaims are not to be thus limited but are to be construed as embodyingall modifications and alternative constructions that may occur to oneskilled in the art which fairly fall within the basic teaching hereinset forth.

What is claimed is:
 1. A path transistor circuit comprising: a pluralityof path transistors connected in parallel and each one having inputterminals, same input signal is being inputted into said input terminalsof said path transistors, and continuities of the plurality of said pathtransistors is being controlled by a plurality of control signals havingan exclusive relationship therebetween; and a plurality of buffers whichdrive drive segments including at least said path transistors andwirings, the drive segments being a plurality of divided ranges eachhaving an equal potential.
 2. The path transistor circuit according toclaim 1, wherein each of said buffer has a driving force capable ofdriving a necessary, sufficient load capacity with a reference to theworst value of the load capacity of said drive segments.
 3. The pathtransistor circuit according to claim 1, wherein said buffers areprovided corresponding to a part of said drive segments.
 4. The pathtransistor circuit according to claim 1, wherein said path transistorcircuit being used as a bit shift circuit applying the select logic ofthe path transistors and operating output bits relative to input bits.5. A path transistor circuit design method comprising: a first step ofdesigning a plurality of path transistors connected in parallel andhaving input terminals, respectively, into which input terminals a sameinput signal is inputted, continuities of the plurality of pathtransistors controlled by a plurality of control signals having anexclusive relationship therebetween; and a second step of designing aplurality of buffers respectively driving drive segments including atleast the plurality of path transistors and wirings, the drive segmentsbeing a plurality of divided ranges each having an equal potential.
 6. Alogic circuit optimization device for optimizing design of a logiccircuit consisting of a plurality of path transistors connected inparallel and having input terminals, respectively, into which inputterminals a same input signal is inputted, said logic circuitoptimization device comprising: a logic specification indication unitwhich indicates logic specifications so that a plurality of controlsignals controlling continuities of the plurality of path transistors,respectively, have an exclusive relationship therebetween; a celllibrary unit which registers a plurality of cell data used to designsaid logic circuit; and an optimization unit which conducts a logiccomposition based on the logic specifications and the cell data, and foroptimizing buffering in said logic circuit.
 7. The logic circuitoptimization device according to claim 6 further comprising a groupingunit which groups said path transistors into a plurality of groups basedon the exclusive relationship, wherein said optimization unit conductslogic composition based on said grouped drive segments, the logicspecifications and the cell data, and optimizes buffering in said logiccircuit.
 8. The logic circuit optimization device according to claim 7wherein said optimization unit optimizes buffering with respect to apart of said drive segments.
 9. The logic circuit optimization deviceaccording to claim 6, wherein said logic circuit is a bit shift circuitapplying the select logic of the path transistors and operating outputbits relative to input bits.
 10. The logic circuit optimization deviceaccording to claim 6, wherein a plurality of the logic circuits areprovided to constitute a macro circuit.
 11. The logic circuitoptimization device according to claim 6, wherein a first cell dataapplying the maximum value of the load capacity of said logic circuitand a second cell data applying the minimum value of the load capacityare registered, as cell data for analyzing the electric characteristicsof the logic circuit, in said cell library unit.
 12. The logic circuitoptimization device according to claim 11, wherein the first and secondcell data are created according to the actual operation of said logiccircuit.
 13. A logic circuit optimization method for optimizing designof a logic circuit consisting of a plurality of path transistorsconnected in parallel and having input terminals, respectively, intowhich input terminals a same input signal is inputted, the methodcharacterized by comprising: a logic specification indication step ofindicating logic specifications so that a plurality of control signalsrespectively controlling continuities of the plurality of pathtransistors have an exclusive relationship therebetween; a registrationstep of registering a plurality of cell data used to design said logiccircuit in a cell library; and an optimization step of conducting logiccomposition based on the logic specifications and the cell data andoptimizing buffering in said logic circuit.
 14. A computer-readablerecording medium recording a logic circuit optimization program appliedto a logic circuit optimization device for optimizing design of a logiccircuit consisting of a plurality of path transistors connected inparallel and having input terminals, respectively, into which inputterminals a same input signal is inputted, the computer-readablerecording medium characterized by recording the logic circuitoptimization program to allow a computer to execute: a logicspecification indication step of indicating logic specifications so thata plurality of control signals respectively controlling continuities ofthe plurality of path transistors have an exclusive relationshiptherebetween; a registration step of registering a plurality of celldata used to design said logic circuit in a cell library; and anoptimization step of conducting logic composition based on the logicspecifications and the cell data and optimizing buffering in said logiccircuit.